How to approach power design for modern computing systems
In today’s computing systems, power-hungry components include FPGAs, CPUs, ASICs, SoCs and now the new ACAP devices (Adaptive Compute Acceleration Platform) which promise step performance improvements in demanding applications such as data centres, wired networks, 5G wireless and automotive driver assist systems.
There is an ongoing battle though, between performance/speed of operation, power consumption, size and the practical considerations of how to efficiently provide power to the circuit elements. Minimising power consumption has always been a high priority in a system designer’s wish-list, as it leads on to smaller devices or systems for a given temperature rise, enabling higher packing density and more functionality – a key expectation from consumers as well as a ‘greener’ product.
In digital devices, power draw is directly related to voltage swing, as internal capacitances are charged and discharged, and ever-faster switching means more transitions per second and hence higher power consumed. To mitigate this, supply voltages to devices have steadily reduced from 5V down to sub-1V. To optimise performance further, sub-sections of devices now have separate supply rails ranging between perhaps 0.85V and lower for the CPU core, a similar voltage for block RAM, 1.35V or 1.5V for DDR memory, 1.8V for auxiliary functions and 3.3V and 5V for legacy I/O requirements. Even if section voltages are similar, they often need to be generated separately to avoid unwanted interactions and so they can be separately enabled and their power up/down sequenced.
Figure 1: A typical 'power tree' for an Altera Stratix FPGA device
Such low voltages mean high currents for a given power, with some CPUs drawing more than 100A on their main supply rail, while other rails in typical devices require current in the range 1A to 25A. High currents pose a problem, though – just 1 milliohm of connection resistance at 100A drops 100mV, way over the allowed variation for a core voltage. It has therefore become a necessity to site DC-DC converters or ‘Point of Load’ (PoL) regulators that provide the power rails, very close to the device. The PoL regulators themselves are powered from a higher bus voltage, typically 5V or 12V, at which level the currents are much lower for the power drawn. System designers will generate a power ‘tree’ diagram to summarise the arrangement (Figure 1, left).
Putting PoL converters close to devices like FPGAs poses problems though; a typical FPGA such as in the Xilinx UltraScaleTM range has more than 1000 BGA connections and is surrounded by supporting devices for I/O as well as a substantial heat sink for the tens of watts produced by the device. Space is therefore at a premium and the PoLs have to fit in where they can. The ideal PoL, therefore, is highly efficient so it can be small without heatsinking requirement, and low profile, so that it can be back-side mounted or even fitted under other components such as board-mounted piggybacks or sub-boards. Of course, it must also provide a precise voltage under static and dynamic conditions, have output control for shutdown and sequencing and be fully protected against shorts, over- and under-voltages, and over-temperature stress. Modern PoL devices will also have communication features, typically over a I2C bus using PMBusTM commands, to set up the device characteristics, either as a one-time adjustment such as for fault detection thresholds or even ‘on-the-fly’ for dynamic adjustment of the output voltage for energy saving schemes. The bus can also typically signal PoL conditions such as load current, temperature and status for remote monitoring.
Typical PoL topology
The basic schematic of a non-isolated PoL converter has not changed over many years (Figure 2, below). Features such as synchronous rectification and multi-phase conversion at higher powers are now standard although there is some variation in control schemes for optimum dynamic performance.
Common elements though are a ‘high-side’ switch, Q1, and a low-side, Q2, switching alternately to supply load current and ‘charge’ inductor L1 in Q1 on-period and discharge its energy through Q2 to the load during Q1 off-period. A controller IC1 samples the output and drives Q1 and Q2 with complementary pulse-width modulated signals to achieve regulation of output voltage by the ‘averaging’ effect of L1 and C2. IC1 also monitors and reacts to abnormal conditions and integrates the external communications function.
Figure 2: PoL basic schematic, single phase type
Dimensioning the components and operating conditions in a PoL converter is a trade-off; the inductor is normally the largest item and defines the overall size or footprint. The inductor and output capacitor can be smaller if the converter switches at higher frequencies, but, like in the FPGA, faster switching of MOSFETs Q1 and Q2 causes more power dissipation, requiring a bigger part to dissipate the heat and keep temperature rise within limits. Advances in MOSFET technology for ON-resistance and switching speed have enabled efficiency improvements though, and now frequencies in the MHz range are feasible.
Implementing a PoL - the ‘old’ way
Figure 3: A traditional discrete implementation of a 6A PoL converter with necessary peripheral components excluding input/output capacitors
The elements of the PoL shown in Figure 2 were initially discrete components which system board designers were able, in theory, to place on the motherboard. PoL design is a particular skill and even with applications information from the PWM controller vendor, it is very difficult to achieve optimum electrical performance when the PoL is mixed in with other motherboard components. Precious motherboard space is also consumed.
Modular PoL vendors have offered solutions that are proven designs with the advantage of a single tested component to source, saving the customer the overhead of design and qualification, as well as procurement, stocking and placement of multiple discrete components. Early modules gave little benefit as they occupied much the same footprint as a discrete solution and were seen as expensive, especially in high production volumes where fixed costs of a discrete solution could be amortised.
More recent modules though have integrated the discrete components into smaller packages with some vertical stacking arrangements giving real footprint savings. SIP versions occupy little space but typically require through-hole soldering and don’t match modern low-profile product designs. Some hybrid products are also available that comprise just the power components of the PoL leaving the user to place the controller on the motherboard, perhaps on the back side, which gives useful extra space saving. Figure 3 (right) shows the components required in a typical discrete implementation of a PoL function, occupying about 50 mm2 for 6A amp rating. The larger input and output filtering capacitors are not included and MOSFET switches are integrated in the controller.
Implementing a PoL converter – a new way
While ‘old style’ motherboards have shrunk down to platforms with much smaller dimensions, such as PCIe, CoM boards, SSD, Edge and IA computing, the market is eager to find more compact solutions for the ever-needed power circuits. On PCIe and CoM boards, for example, the power section can occupy up to 20% of board space.
Rather than taking existing discrete components and just trying to assemble them in a different way to achieve incremental improvement in size and performance, TDK has taken a ‘clean whiteboard’ approach with the design of its new µPOL™ range of modular PoLs, providing power for 5W to 150W systems (Figure 4, below). Several proprietary, patented technologies have been combined to yield a dramatic improvement in footprint to just 25% of competitors’, with a current density 4 x better.
Figure 4: The innovative µPOL™ PoL converter from TDK with a
The FS1406 series, initially available in 3A, 4A and 6A versions will be expanded in the future to 25A and on to 100A. The products available now are in a tiny 3.3mm x 3.3mm package just 1.5mm tall for placement in height-constrained areas such as on the backside of the motherboard or under other components such as heatsinks and daughterboards. Power density achieved is a class-leading 1W/mm3.
Like competing PoLs, external input and output capacitors need to be added for a full implementation but these are small due to the high switching frequency employed. From a system point of view, it is better to add the capacitors externally, as they can be dimensioned for the exact voltage and load transient response requirements of the application. Input and output capacitors included in a PoL would otherwise have to be sized for the highest possible load and highest possible input and adjusted output voltage, adding unnecessary cost and board space used.
Unlike the discrete PoL solution in Figure 3, with the TDK µPOL™ in a minimal configuration, apart from input/output capacitors, no other components are required, such as compensation networks, output setting resistors, bootstrap or pin decoupling capacitors.
Key to the improvements achieved are TDK’s long-established and industry-leading thin film inductor technology and a new technique dubbed SESUB or Semiconductor Embedded in SUBstrate which integrates the MOSFETs and control IC into the layers of a 250µm thick substrate with the inductor and two small bypass capacitors placed on top.
With a high efficiency design, TDK has used its packaging expertise to control thermal characteristics so that heat from the IC and inductor are effectively led to the substrate terminations and to the motherboard. This is so effective that at full 6A output, the module temperature rise is just 41°C for a part with 12V input and 1.8V output. Although this depends on heat flow to the motherboard, TDK has shown that multiple µPOLs can be placed with just a few millimetres separation with no degradation in power rating.
µPOL™ system benefits
The tiny footprint of the µPOL™ enables the smallest of spaces to be utilised for voltage regulation close to the target device, and applications are scalable, as the 3A to 6A parts have the same footprint. Output voltage is selectable from 0.4V to 5V and input voltage range is 4.5V to 16V with a single supply and 2.5 to 16V with an extra auxiliary supply providing a higher bias voltage.
The integrated monitoring and control functionality of the µPOL™ also adds significant system benefits: for example, each features a ‘power good’ output and ‘enable’ input which can be utilised for power-up and -down output sequencing of multiple µPOLs with ‘ratiometric’ and ‘simultaneous’ schemes available. Protection is comprehensive with output over-voltage, input under-voltage and output over-current or short circuit monitored, all with selectable thresholds, with ‘hiccup’ mode shutdown. The devices operate over the range -40°C to +125°C and have programmable thermal shutdown with auto recovery.
The built-in I2C interface which supports Fast and Fast Plus modes, enables a wide range of settings via PMBus™ commands:
- Settable output voltage, 0.4V to 5V with 5mV resolution (fixed input versions initially available – variant dependent)
- Output voltage trim, (+/- 0.5% initial accuracy)
- Optional soft start and stop rates 0.5mV/µs or 1mV/µs
- Adjustable PGood Threshold: 85%, 90% and 95% of Vout
- Adjustable OVP threshold: 105%, 110%, 115% and 120% of Vout
- Adjustable OVP scheme: Latch, Unlatch
- Adjustable OCP threshold: up to 8A with 250mA resolution
- Adjustable OTP threshold: 75oC, 85oC, 125oC and 145oC
- Selectable ‘continuous’ (CCM) or ‘discontinuous’ (DCM) operating modes for EMI and efficiency optimization
With a wide range of devices, options and settings, system designers can ‘tune’ applications using the µPOL™ for minimum system cost and maximum functionality.
Figure 5 shows the TDK µPOL™ configured for Vin = 12V, Vout = 1.8V and Iout = 6A with a requirement that ripple voltage is less than +/-1% pp of Vout and there is a maximum excursion of +/-3% of Vout with a 3A load step. The µPOL™ part is FS1406 and 2 x 22µF capacitors are initially chosen for both Cin and Cout. Switching frequency Fsw is 2MHz.
Figure 5: The TDK FS1406 µPOL™ in a typical application
Selection of input capacitor type depends on ripple current handling IRMS. In a buck converter operating at duty cycle D, this is given by:
In this application Iout is 6A and D = Vout/Vin = 0.15, giving IRMS = 2.14A which is easily handled by two 22µF, 16V capacitors type TDK C3216X5R1C226M160AB.
For the output capacitors, there is a minimum number required NMIN to meet the target ripple Δ Vout given by:
TDK MLCC capacitors C2012X5R0J226K125AB have an ESR of 3 milliohms, an ESL of 0.44nH and an effective capacitance of 12µF at 1.8V. Solving, NMIN is 1.27 so 2 capacitors as assumed is adequate.
The minimum number of capacitors to meet the load transient response ΔVoutmax with load step ΔIout is given by:
Solving again with 12µF, NMIN is 0.4 so two TDK capacitors C2012X5R0J226K125AB is a good solution.
The resultant ripple and load transient response plots are given in Figures 6 and 7 showing just 15.19mV pp ripple or 0.8%, and about 30mV excursion or +/-1.7% with load steps.
Figure 6: Ripple achieved in application
Figure 7: Transient load response showing
At higher output voltages, the minimum number of output 22µF capacitors decreases to meet the same ripple and transient specification and above 2.25V output, just one is required.
The TDK µPOL™ - breakthrough performance with comprehensive support
To support design-in of the µPOL™, TDK provides a suite of tools including general purpose evaluation boards with interfaces to access the I2C bus, with an easy-to-use GUI to set up the parts. Moreover, ‘Power Strip Design Boards’ are also available with up to eight µPOLTM units fitted to provide all the rails, including sequencing capability boards, for Xilinx Spartan 7, Artix 7, Zynq 7, Zynq UltraScale+, Zynq UltraScale+ RFSoC, Versal ACAP (Versal Prime Series) and other FPGAs from vendors such as Altera, NXP (i.Mx8, LS series), Marvell/Cavium and Microsemi. For quick implementation, schematics are provided along with PCB ‘layout snippets’ for ORCAD/Allegro, Altium and Mentor PADs+/Xpedition CAD programs. ‘Ready to go’ power subsystem solutions for vendor FPGAs are available from TDK and, as a Xilinx ‘Alliance Program Certified member’, TDK has generated complete reference designs for FPGAs such as the Zynq7 series.
The µPOL™ parts from TDK are a breakthrough in power density and footprint size for PoLs up to six amps with higher rated parts in the pipeline offering similar benefits. The ‘plug and play’ solution saves space and design time without compromising performance and as a system rather than component solution, the µPOL™ reduces external component requirements and their associated board space, saving overall cost. Ability to program performance over the I2C bus gives design flexibility and time to market is also quicker with the excellent design tool support from TDK.
Evaluation board demos are available from Avnet Abacus. Visit the TDK µPOL™ page to find out more and request yours. Alternatively, our technical specialists are on hand to discuss your design requirements with you. Click the Ask an Expert button to get in touch.